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rev. 1.4 april 2007 ddr2 sdram sodimm 1 of 20 ddr2 unbuffered sodimm 200pin unbuffered sodimm based on 512mb e-die 64bit non-ecc * samsung electronics reserves the right to ch ange products or specification without notice. information in this document is provided in relation to samsung products, and is subject to change without notice. nothing in this document shall be construed as granting any license, express or implied, by estoppel or otherwise, to any intellectual property rights in samsung products or technology. all information in this document is provided on as "as is" basis without guarantee or warranty of any kind. 1. for updates or additional information about sa msung products, contact your nearest samsung office. 2. samsung products are not intended for use in life support, critical care, me dical, safety equipment, or similar applications where product failure couldresult in loss of life or personal or physical harm, or any military or defense application, or any governmen tal procurement to which special terms or provisions may apply. 60fbga & 84fbga with pb-free (rohs compliant)
rev. 1.4 april 2007 ddr2 sdram sodimm 2 of 20 table of contents 1.0 ddr2 unbuffered sodi mm ordering information ..... ................ ................. ................ .............. 4 2.0 features ............ ................ ................. .............. .............. .............. .............. ............. ............. ......... 4 3.0 address configuration .... ................. ................ ................ ................. ................ ............... ........... 4 4.0 pin configurations (front side/back side) ..... ................ ................. ................ .............. ............ 5 5.0 pin description .......... ................. ................ ................ ................. ................ ............... ........... ....... 5 6.0 input/output functional desc ription ............... ................ .............. ............... .............. ............. ... 6 7.0 functional block diagram : ................ ................ ................. ................ ................. .............. ......... 7 7.1 256mb, 32mx64 module(m470t3354ez3) ................. ................. ................ .............. .............. ............ 7 7.2 512mb, 64mx64 module(m470t6554ez3) ................ ................. ................ .............. .............. ............ 8 7.3 1gb, 128mx64 module(m470t2953ez3) .............. ................ ................ ................. ................ ............ 9 8.0 absolute maximum dc ratings ....... ................ ................ .............. ............... .............. ............. .10 9.0 ac & dc operating conditions ....... ................ ................ .............. ............... .............. ............ .. 10 9.1recommended dc operating conditions (sstl - 1.8) ................ .............. .............. .............. ............ 10 9.2 operating temperature condition ................ ................ ................. ................ ................. .............. 11 9.3 input dc logic level ................ ................. .............. .............. .............. .............. .............. ............ 11 9.4 input ac logic level ................ ................. .............. .............. .............. .............. .............. ............ 11 9.5 ac input test conditions ................. ................. ................ ................ ................. .............. ............ 11 10.0 idd specification parameters defi nition ........ ................. .............. .............. .............. ............ 12 11.0 operating current table .......... ................ ................ .............. ............... .............. ............. ........ 13 11.1 m470t3354ez3 : 32mx64 256mb module ............... ................. .............. .............. .............. ............ 13 11.2 m470t6554ez3 : 64mx64 512mb module ............... ................. .............. .............. .............. ............ 13 11.3 m470t2953ez3 : 128mx64 1gb module ............... ................ ................. .............. .............. ............ 14 12.0 input/output capacitance ......... ................ ................. .............. .............. .............. ............. ...... 15 13.0 electrical characteristics & ac timing for ddr2-800/667/533/400 ........... .............. ............ 15 13.1 refresh pa rameters by device density ............... ................ ................. .............. .............. ............ 15 13.2 speed bins and cl, trcd, trp, trc and tras for corresponding bin .............. ................. .............. 15 13.3 timing parameters by speed grade .............. ................. ................ ................. ................ ............ 16 14.0 physical dimensions : .......... ................. ................ ................ ............... .............. ............ ......... 18 14.1 32mbx16 based 32mx64 module(1 rank) (m470t3354ez3) .............. ................ ................. .............. 18 14.2 32mbx16 based 64mx64 module(2 rank)( m470t6554ez3) .............. ................ ................. .............. 19 14.3 64mbx8 based 128mx64 module(2 ranks) (m470t2953ez3) ............. ................ ................. .............. 20
rev. 1.4 april 2007 ddr2 sdram sodimm 3 of 20 revision history revision month year history 0.1 march 2006 - initial release 1.0 september 2006 - revised the idd values 1.1 september 2006 - added the vddspd values - added ddr2-800 cl6 1.2 january 2007 - corrected typo 1.3 april 2007 - added the bookmark 1.4 april 2007 - corrected typo
rev. 1.4 april 2007 ddr2 sdram sodimm 4 of 20 note : 1. ?z? of part number(11th digit) stand for lead-free products. 2. ?3? of part number(12th digit) stand for dummy pad pcb products. part number density organization component composition number of rank height m470t3354ez3-c(l)e7/f7/e6/d5/cc 256mb 32mx64 32mx16(k4t51163qe)*4 1 30mm m470t6554ez3-c(l)e7/f7/e6/d5/cc 512mb 64mx64 32mx16(k4t51163qe)*8 2 30mm m470t2953ez3-c(l)e7/f7/e6/d5/cc 1gb 128mx64 64mx8(k4t51083qe)*16 2 30mm ? performance range ? jedec standard 1.8v 0.1v power supply ?v ddq = 1.8v 0.1v ? 200 mhz f ck for 400mb/sec/pin, 267mhz f ck for 533mb/sec/pin, 333mhz f ck for 667mb/sec/pin, 400mhz f ck for 800mb/sec/pin ?4 banks ? posted cas ? programmable cas latency: 3, 4, 5, 6 ? programmable additive latency: 0, 1 , 2 , 3, 4, 5 ? write latency(wl) = read latency(rl) -1 ? burst length: 4 , 8(interleave/nibble sequential) ? programmable sequential / interleave burst mode ? bi-directional differential data-strobe (s ingle-ended data-strobe is an optional feature) ? off-chip driver(ocd) impedance adjustment ? on die termination with selectable values(50/75/150 ohms or disable) ? pasr(partial array self refresh) ? average refresh period 7.8us at lower than a t case 85 c, 3.9us at 85 c < t case < 95 c - support high temperature self-refresh rate enable feature ? package: 60ball fbga - 64mx8 , 84ball fbga - 32mx16 ? all of lead-free products are compliant for rohs note: for detailed ddr2 sdram operation, please refer to samsung?s device operation & timing diagram. e7 (ddr2-800) f7 (ddr2-800) e6 (ddr2-667) d5 (ddr2-533) cc (ddr2-400) unit speed@cl3 400 - 400 400 400 mbps speed@cl4 533 533 533 533 400 mbps speed@cl5 800 667 667 533 -mbps speed@cl6 - 800 - - -mbps cl-trcd-trp 5-5-5 6-6-6 5-5-5 4-4-4 3-3-3 ck organization row address column address bank address auto precharge 64mx8(512mb) based module a0-a13 a0-a9 ba0-ba1 a10 32mx16(512mb) based module a0-a12 a0-a9 ba0-ba1 a10 1.0 ddr2 unbuffered so dimm ordering information 2.0 features 3.0 address configuration
rev. 1.4 april 2007 ddr2 sdram sodimm 5 of 20 note : nc = no connect; nc, test(pin 163)is for bus anal ysis tool and is not connect ed on normal memory modules. pin front pin back pin front pin back pin front pin back pin front pin back 1 v ref 2 v ss 51 dqs2 52 dm2 101 a1 102 a0 151 dq42 152 dq46 3 v ss 4dq453 v ss 54 v ss 103 v dd 104 v dd 153 dq43 154 dq47 5 dq0 6 dq5 55 dq18 56 dq22 105 a10/ap 106 ba1 155 v ss 156 v ss 7dq18 v ss 57 dq19 58 dq23 107 ba0 108 ras 157 dq48 158 dq52 9 v ss 10 dm0 59 v ss 60 v ss 109 we 110 s 0 159 dq49 160 dq53 11 dqs 012 v ss 61 dq24 62 dq28 111 v dd 112 v dd 161 v ss 162 v ss 13dqs014 dq6 63dq2564dq29113cas 114 odt0 163 nc, test 164 ck1 15 v ss 16 dq7 65 v ss 66 v ss 115 nc/s 1 116 a13 165 v ss 166 ck 1 17 dq2 18 v ss 67 dm3 68 dqs 3117 v dd 118 v dd 167 dqs 6 168 v ss 19 dq3 20 dq12 69 nc 70 dqs3 119 nc/odt1 120 nc 169 dqs6 170 dm6 21 v ss 22 dq13 71 v ss 72 v ss 121 v ss 122 v ss 171 v ss 172 v ss 23 dq8 24 v ss 73 dq26 74 dq30 123 dq32 124 dq36 173 dq50 174 dq54 25 dq9 26 dm1 75 dq27 76 dq31 125 dq33 126 dq37 175 dq51 176 dq55 27 v ss 28 v ss 77 v ss 78 v ss 127 v ss 128 v ss 177 v ss 178 v ss 29 dqs 1 30 ck0 79 cke0 80 nc/cke1 129 dqs 4 130 dm4 179 dq56 180 dq60 31 dqs1 32 ck 081 v dd 82 v dd 131dqs4132 v ss 181 dq57 182 dq61 33 v ss 34 v ss 83 nc 84 nc 133 v ss 134dq38183 v ss 184 v ss 35 dq10 36 dq14 85 nc/ba2 86 nc 135 dq34 136 dq39 185 dm7 186 dqs 7 37 dq11 38 dq15 87 v dd 88 v dd 137 dq35 138 v ss 187 v ss 188 dqs7 39 v ss 40 v ss 89 a12 90 a11 139 v ss 140 dq44 189 dq58 190 v ss 41 v ss 42 v ss 91 a9 92 a7 141 dq40 142 dq45 191 dq59 192 dq62 43 dq16 44 dq20 93 a8 94 a6 143 dq41 144 v ss 193 v ss 194 dq63 45 dq17 46 dq21 95 v dd 96 v dd 145 v ss 146 dqs 5 195 sda 196 v ss 47 v ss 48 v ss 97 a5 98 a4 147 dm5 148 dqs5 197 scl 198 sa0 49 dqs 2 50 nc 99 a3 100 a2 149 v ss 150 v ss 199 v dd spd 200 sa1 pin name function pin name function ck0,ck1 clock inputs, positive line sda spd data input/output ck 0,ck 1 clock inputs, negative line sa1,sa0 spd address cke0,cke1 clock enables dq0~dq63 data input/output ras row address strobe dm0~dm7 data masks cas column address strobe dqs0~dqs7 data strobes we write enable dqs 0~dqs 7 data strobes complement s 0,s 1 chip selects test logic analyzer specific test pin (no connect on so-dimm) a0~a9, a11~a13 address inputs v dd core and i/o power a10/ap address input/autoprecharge v ss ground ba0,ba1 sdram bank address v ref input/output reference odt0,odt1 on-die termination control v dd spd spd power scl serial presence detect(spd) cl ock input nc spare pins, no connect 4.0 pin configur ations (front side/back side) 5.0 pin description
rev. 1.4 april 2007 ddr2 sdram sodimm 6 of 20 symbol type function ck0-ck1 ck 0-ck 1 input the system clock inputs. all address and command lines are samp led on the cross point of the rising edge of ck and fall- ing edge of ck . a delay locked loop (dll) circuit is driven from t he clock input and output timing for read operations is synchronized to the input clock. cke0-cke1 input activates the ddr2 sdram ck signal when high and deactivate s the ck signal when low, by deactivating the clocks, cke low initiates the power down mode or the self refesh mode. s 0-s 1 input enables the associated ddr2 sdram command decoder w hen low and disables the command decoder when high. when the command decoder is disabled, new commands are ignored but previous operat ions continue. rank 0 is selected by s 0, rank 1 is selected by s 1. ranks are also called ?physical banks?. ras , cas , we input when sampled at the cross point of the rising edge of ck and falling edge of ck , cas , ras , and we define the operation to be executed by the sdram. ba0~ba1 input selects which ddr2 sdram internal bank is activated. odt0~odt1 input asserts on-die termination for dq, dm, dqs, and dqs signals if enabled via the ddr2 sdram extended mode register set (emrs). a0~a9, a10/ap, a11~a13 input during a bank activate command cycle, defines the row address when sampled at the cross point of the rising edge of ck and falling edge of ck. during a read or write command cycle, defines the column address when sampled at the cross point of the rising edge of ck and falling edge of ck. in addition to the column address, ap is used to invoke autopre- charge operation at the end of the burst read or write cycle. if ap is high, autoprecharge is selected and ba0-ban defines the bank to be precharged. if ap is low, autoprecharge is dis abled. during a precharge command cycle, ap is used in con- junction with ba0-ban to control which bank(s) to precharge. if ap is high, all banks will be pecharged regardiess of the state of ba0-ban inputs. if ap is low, then ba0-b an are used to define which bank to precharge. dq0~dq63 in/out data input/output pins. dm0~dm7 input the data write masks, associated with one data byte. in write mode, dm operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high. in read mode, dm lines have no effect. dqs0~dqs7 dqs 0~dqs 7 in/out the data strobes, associated with one data byte, sourced with da ta transfers. in write mode, the data strobe is sourced by the controller and is centered in the data window. in read m ode, the data strobe is sourced by the ddr2 sdrams and is sent at the leading edge of the data window. dqs signals are complements, and timing is relative to the crosspoint of respective dqs and dqs if the module is to be operated in single ended strobe mode, all dqs signals must be tied on the system board to vss and ddr2 sdram mode registers program med appropriately. v dd ,v dd spd,v ss supply power supplies for core, i/o, serial presence detect, and ground for the module. sda in/out this is a bidirectional pin used to tr ansfer data into or out of the spd eeprom. a resistor must be connected to v dd to act as a pull up. scl input this signal is used to clock data into and out of the spd eeprom. a resistor may be connected from scl to v dd to act as a pull up. sa0~sa1 input address pins used to select the serial presence detect base address. test in/out the test pin is reserved for bus analysis t ools and is not connected on norma l memory modules(so-dimms). 6.0 input/output functional description
rev. 1.4 april 2007 ddr2 sdram sodimm 7 of 20 (populated as 1 rank of x16 ddr2 sdrams) s 0 dqs1 dqs 1 dm1 cs dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d0 ldqs ldqs ldm dqs0 dqs 0 dm0 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 udqs udqs udm dqs5 dqs 5 dm5 cs dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d2 ldqs ldqs ldm dqs4 dqs 4 dm4 dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 udqs udqs udm dqs3 dqs 3 dm3 cs dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d1 ldqs ldqs ldm dqs2 dqs 2 dm2 dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 udqs udqs udm dqs7 dqs 7 dm7 cs dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d3 ldqs ldqs ldm dqs6 dqs 6 dm6 dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 udqs udqs udm o d t c k e o d t c k e o d t c k e o d t c k e odt0 cke0 spd sa0 scl sda v ss ddr2 sdrams d0 - d3, spd v ref ddr2 sdrams d0 - d3 ddr2 sdrams d0 - d3, v dd and v dd q v dd v dd spd serial pd wp sa1 scl a0 a1 a2 a0 - a13 ddr2 sdrams d0 - d3 ras ddr2 sdrams d0 - d3 cas ddr2 sdrams d0 - d3 we ddr2 sdrams d0 - d3 ba0 - ba1 ddr2 sdrams d0 - d3 3 ? + 5% note : 1. dq,dm, dqs/dqs resistors : 22 ohms 5%. 2. bax, ax, ras , cas , we resistors : 3.0 ohms 5% . * wire per clock loading table/wiring diagrams * clock wiring clock input ddr2 sdrams *ck0/ck0 *ck1/ck1 2 ddr2 sdrams 2 ddr2 sdrams 3 ? + 5% 7.0 functional block diagram : 7.1 256mb, 32mx64 module - m470t3354ez3
rev. 1.4 april 2007 ddr2 sdram sodimm 8 of 20 s 0 dqs1 dqs 1 dm1 cs dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d0 ldqs ldqs ldm dqs0 dqs 0 dm0 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 udqs udqs udm dqs5 dqs 5 dm5 cs dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d2 ldqs ldqs ldm dqs4 dqs 4 dm4 dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 udqs udqs udm dqs3 dqs 3 dm3 cs dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d1 ldqs ldqs ldm dqs2 dqs 2 dm2 dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 udqs udqs udm dqs7 dqs 7 dm7 cs dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d3 ldqs ldqs ldm i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 udqs udqs udm c k e o d t c k e o d t c k e o d t c k e o d t cs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d4 ldqs ldqs ldm i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 udqs udqs udm cs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d5 ldqs ldqs ldm i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 udqs udqs udm c k e o d t c k e o d t cs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d6 ldqs ldqs ldm i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 udqs udqs udm cs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d7 ldqs ldqs ldm i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 udqs udqs udm c k e o d t c k e o d t s 1 cke0 cke1 odt0 odt1 spd sa0 scl sda v ss ddr2 sdrams d0 - d7, spd v ref ddr2 sdrams d0 - d7 ddr2 sdrams d0 - d7, v dd and v dd q v dd v dd spd serial pd wp sa1 scl a0 a1 a2 a0 - a13 ddr2 sdrams d0 - d7 ras ddr2 sdrams d0 - d7 cas ddr2 sdrams d0 - d7 we ddr2 sdrams d0 - d7 ba0 - ba1 ddr2 sdrams d0 - d7 3 ? + 5% note : 1. dq,dm, dqs/dqs resistors : 22 ohms 5%. 2. bax, ax, ras , cas , we resistors : 3.0 ohms 5%. * wire per clock loading table/wiring diagrams * clock wiring clock input ddr2 sdrams *ck0/ck0 *ck1/ck1 4 ddr2 sdrams 4 ddr2 sdrams 3 ? + 5% dqs6 dqs 6 dm6 dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 (populated as 2 rank of x16 ddr2 sdrams) 7.2 512mb, 64mx64 module - m470t6554ez3
rev. 1.4 april 2007 ddr2 sdram sodimm 9 of 20 odt0 cke0 s 1 odt1 cke1 spd sa0 scl sda v ss ddr2 sdrams d0 - d15, spd v ref ddr2 sdrams d0 - d15 ddr2 sdrams d0 - d15, v dd and v dd q v dd v dd spd serial pd wp sa1 scl a0 a1 a2 a0 - a13 ddr2 sdrams d0 - d15 ras ddr2 sdrams d0 - d15 cas ddr2 sdrams d0 - d15 we ddr2 sdrams d0 - d15 ba0 - ba1 ddr2 sdrams d0 - d15 10 ? + 5% 3 ? + 5% s 0 dqs1 dqs 1 dm1 cs 0 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d0 dqs dqs dm dqs0 dqs 0 dm0 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 dqs dqs dm dqs5 dqs 5 dm5 dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d4 dqs dqs dm dqs4 dqs 4 dm4 dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 dqs dqs dm dqs3 dqs 3 dm3 dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqs dqs dm dqs2 dqs 2 dm2 dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 dqs dqs dm dqs7 dqs 7 dm7 dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqs dqs dm dqs6 dqs 6 dm6 dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 dqs dqs dm o d t 0 c k e 0 cs 1 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d8 dqs dqs dm i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 dqs dqs dm i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqs dqs dm i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 dqs dqs dm o d t 1 c k e 1 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d12 dqs dqs dm i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 dqs dqs dm i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqs dqs dm i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 dqs dqs dm cs 0 o d t 0 c k e 0 cs 1 o d t 1 c k e 1 cs 0 d1 d5 o d t 0 c k e 0 cs 1 d9 o d t 1 c k e 1 d13 cs 0 o d t 0 c k e 0 cs 1 o d t 1 c k e 1 cs 0 d2 d6 o d t 0 c k e 0 cs 1 d10 o d t 1 c k e 1 d14 cs 0 o d t 0 c k e 0 cs 1 o d t 1 c k e 1 cs 0 d3 d7 o d t 0 c k e 0 cs 1 d11 o d t 1 c k e 1 d15 cs 0 o d t 0 c k e 0 cs 1 o d t 1 c k e 1 note : 1. dq,dm, dqs/dqs resistors : 22 ohms 5%. 2. bax, ax, ras , cas , we resistors : 10.0 ohms 5%. * wire per clock loading table/wiring diagrams * clock wiring clock input ddr2 sdrams *ck0/ck0 *ck1/ck1 8 ddr2 sdrams 8 ddr2 sdrams (populated as 2 ranks of x8 ddr2 sdrams) 7.3 1gb, 128mx64 module - m470t2953ez3
rev. 1.4 april 2007 ddr2 sdram sodimm 10 of 20 note : there is no specific device v dd supply voltage requirement for sstl-1.8 co mpliance. however under all conditions v ddq must be less than or equal to v dd . 1. the value of v ref may be selected by the user to pr ovide optimum noise margin in the system. typically the value of v ref is expected to be about 0.5 x v ddq of the transmitting device and v ref is expected to track variations in v ddq . 2. peak to peak ac noise on v ref may not exceed +/-2% v ref (dc). 3. v tt of transmitting device must track v ref of receiving device. 4. ac parameters are measured with v dd , v ddq and v ddl tied together. 5. so-dimms that include an optional temperature sensor may require a restricted v dd spd operating voltage range for proper operation of the temperature sensor. refer to the thermal sensor specification for details regarding the supported voltage range. all other functions of the so-dimm spd are supported across the full v dd spd range. symbol parameter rating units notes min. typ. max. v dd supply voltage 1.7 1.8 1.9 v v ddl supply voltage for dll 1.7 1.8 1.9 v 4 v ddq supply voltage for output 1.7 1.8 1.9 v 4 v ref input reference voltage 0.49*v ddq 0.50*v ddq 0.51*v ddq mv 1,2 v tt termination voltage v ref -0.04 v ref v ref +0.04 v 3 symbol parameter rating units notes min. max. v dd spd core supply voltage 1.7 3.6 v 5 8.0 absolute maximum dc ratings note : 1. stresses greater than those listed under ?absolute maximum rati ngs? may cause permanent damage to the device. this is a stre ss rating only and functional operation of the device at these or any other conditi ons above those indicated in the operational sections of this s pecification is not implied. exposure to absolute maximum rating condition s for extended periods may affect reliability. 2. storage temperature is the case surface temperature on the center/top side of the dram. for the measurement conditions, plea se refer to jesd51-2 standard. symbol parameter rating units notes v dd voltage on v dd pin relative to v ss - 1.0 v ~ 2.3 v v 1 v ddq voltage on v ddq pin relative to v ss - 0.5 v ~ 2.3 v v 1 v ddl voltage on v ddl pin relative to v ss - 0.5 v ~ 2.3 v v 1 v in, v out voltage on any pin relative to v ss - 0.5 v ~ 2.3 v v 1 t stg storage temperature -55 to +100 c 1, 2 9.0 ac & dc op erating conditions 9.1recommended dc operating conditions (sstl - 1.8)
rev. 1.4 april 2007 ddr2 sdram sodimm 11 of 20 v ddq v ih (ac) min v ih (dc) min v ref v il (dc) max v il (ac) max v ss < ac input test signal waveform > v swing(max) delta tr delta tf v ref - v il (ac) max delta tf falling slew = rising slew = v ih (ac) min - v ref delta tr 9.2 operating temperature condition 1. operating temperature is the case surface temperature on the center/top side of the dram. for the measurement conditions, ple ase refer to jesd51.2 standard. 2. at 85 - 95 c operation temperature range, doubling refresh commands in frequenc y to a 32ms period ( trefi=3.9 us ) is required, and to ent er to self refresh mode at this temperature range, an emrs command is required to change internal refresh rate. 9.3 input dc logic level 9.4 input ac logic level 9.5 ac input test conditions note: 1. input waveform timing is referenced to the input signal crossing through the v ih/il (ac) level applied to the device under test. 2. the input signal minimum slew rate is to be maintained over the range from v ref to v ih (ac) min for rising edges and the range from v ref to v il (ac) max for falling edges as shown in the below figure. 3. ac timings are referenced with input waveforms switching from v il (ac) to v ih (ac) on the positive transitions and v ih (ac) to v il (ac) on the negative transitions. symbol parameter rating units notes toper operating temperature 0 to 95 c 1, 2 symbol parameter min. max. units notes v ih (dc) dc input logic high v ref + 0.125 v ddq + 0.3 v v il (dc) dc input logic low - 0.3 v ref - 0.125 v symbol parameter ddr2-400, ddr2-533 ddr2-667, ddr2-800 units min. max. min. max. v ih (ac) ac input logic high v ref + 0.250 - v ref + 0.200 v v il (ac) ac input logic low - v ref - 0.250 v ref - 0.200 v symbol condition value units notes v ref input reference voltage 0.5 * v ddq v1 v swing(max) input signal maximum peak to peak swing 1.0 v 1 slew input signal minimum slew rate 1.0 v/ns 2, 3
rev. 1.4 april 2007 ddr2 sdram sodimm 12 of 20 (idd values are for full operating range of voltage and temperature) symbol proposed conditions units notes idd0 operating one bank active-precharge current ; t ck = t ck(idd), t rc = t rc(idd), t ras = t rasmin(idd); cke is high, cs\ is high between valid commands; address bus inputs are switching; data bus inputs are switching ma idd1 operating one bank active-read-precharge current ; iout = 0ma; bl = 4, cl = cl(idd), al = 0; t ck = t ck(idd), t rc = t rc (idd), t ras = t rasmin(idd), t rcd = t rcd(idd); cke is high, cs\ is high between valid comm ands; address bus inputs are switching; data pattern is same as idd4w ma idd2p precharge power-down current ; all banks idle; t ck = t ck(idd); cke is low; other control and address bus inputs are stable; data bus inputs are floating ma idd2q precharge quiet standby current ; all banks idle; t ck = t ck(idd); cke is high, cs\ is high; other control and address bus inputs are stable; data bus inputs are floating ma idd2n precharge standby current ; all banks idle; t ck = t ck(idd); cke is high, cs\ is high; other control and address bus inputs are switching; data bus inputs are switching ma idd3p active power-down current ; all banks open; t ck = t ck(idd); cke is low; other control and address bus inputs are stable; data bus inputs are floating fast pdn exit mrs(12) = 0ma ma slow pdn exit mrs(12) = 1ma ma idd3n active standby current ; all banks open; t ck = t ck(idd), t ras = t rasmax(idd), t rp = t rp(idd); cke is high, cs\ is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching ma idd4w operating burst write current ; all banks open, continuous burst writes; bl = 4, cl = cl(idd), al = 0; t ck = t ck(idd), t ras = t rasmax(idd), t rp = t rp(idd); cke is high, cs\ is high between valid co mmands; address bus inputs are switching; data bus inputs are switching ma idd4r operating burst read current ; all banks open, continuous burst reads, iout = 0ma; bl = 4, cl = cl(idd), al = 0; t ck = t ck(idd), t ras = t ras- max(idd), t rp = t rp(idd); cke is high, cs\ is high between va lid commands; address bus inputs are switch- ing; data pattern is same as idd4w ma idd5b burst auto refresh current ; t ck = t ck(idd); refresh command at every t rfc(idd) interval; cke is high, cs\ is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching ma idd6 self refresh current ; ck and ck\ at 0v; cke 0.2v; other control and address bus inputs are floating; data bus inputs are floating normal ma low power ma idd7 operating bank interleave read current ; all bank interleaving reads, iout = 0ma; bl = 4, cl = cl(idd), al = t rcd(idd)-1* t ck(idd); t ck = t ck(idd), t rc = t rc(idd), t rrd = t rrd(idd), t faw = t faw(idd), t rcd = 1* t ck(idd); cke is high, cs\ is high between valid commands; address bus inputs are stable during deselects; data pattern is same as idd4r; refer to the fol- lowing page for detailed timing conditions ma 10.0 idd specification pa rameters definition
rev. 1.4 april 2007 ddr2 sdram sodimm 13 of 20 (t a =0 o c, vdd= 1.9v) * module idd was calculated on the basis of component idd and can be differently measured ac cording to dq loading cap. symbol 800@cl=5 800@cl=6 667@cl=5 533@cl=4 400@cl=3 unit notes ce7 le7 cf7 lf7 ce6 le6 cd5 ld5 ccc lcc idd0 380 380 360 360 360 ma idd1 460 460 440 420 420 ma idd2p32203220322032183218ma idd2q 140 140 140 120 120 ma idd2n 160 160 160 140 140 ma idd3p-f 120 120 120 120 120 ma idd3p-s4848484848ma idd3n 240 240 220 200 200 ma idd4w 540 540 480 420 400 ma idd4r 760 760 680 560 540 ma idd5 460 460 440 440 440 ma idd6 32 16 32 16 32 16 32 16 32 16 ma idd7 1,120 1,120 960 960 860 ma (t a =0 o c, vdd= 1.9v) * module idd was calculated on the basis of component idd and can be differently measured ac cording to dq loading cap. symbol 800@cl=5 800@cl=6 667@cl=5 533@cl=4 400@cl=3 unit notes ce7 le7 cf7 lf7 ce6 le6 cd5 ld5 ccc lcc idd0 540 540 520 500 500 ma idd1 620 620 600 560 560 ma idd2p64406440644064366436ma idd2q 280 280 280 240 240 ma idd2n 320 320 320 280 280 ma idd3p-f 240 240 240 240 240 ma idd3p-s9696969696ma idd3n 400 400 380 340 340 ma idd4w 700 700 640 560 540 ma idd4r 920 920 840 700 680 ma idd5 620 620 600 580 580 ma idd6 64 32 64 32 64 32 64 32 64 32 ma idd7 1,280 1,280 1,120 1,100 1,000 ma 11.0 operating current table 11.1 m470t3354ez3 : 32mx64 256mb module 11.2 m470t6554ez3 : 64mx64 512mb module
rev. 1.4 april 2007 ddr2 sdram sodimm 14 of 20 (t a =0 o c, vdd= 1.9v) * module idd was calculated on the basis of component idd and can be differently measured ac cording to dq loading cap. symbol 800@cl=5 800@cl=6 667@cl=5 533@cl=4 400@cl=3 unit notes ce7 le7 cf7 lf7 ce6 le6 cd5 ld5 ccc lcc idd0 1,000 1,000 920 880 840 ma idd1 1,080 1,080 1,040 960 960 ma idd2p 128 80 128 80 128 80 128 72 128 72 ma idd2q 560 560 560 480 480 ma idd2n 640 640 640 560 560 ma idd3p-f 480 480 480 480 480 ma idd3p-s 192 192 192 192 192 ma idd3n 800 800 760 680 680 ma idd4w 1,240 1,240 1,160 1,000 960 ma idd4r 1,480 1,480 1,400 1,160 1,080 ma idd5 1,240 1,240 1,200 1,160 1,120 ma idd6 128 64 128 64 128 64 128 64 128 64 ma idd7 2,040 2,040 1,760 1,720 1,720 ma 11.3 m470t2953ez3 : 128mx64 1gb module
rev. 1.4 april 2007 ddr2 sdram sodimm 15 of 20 (vdd=1.8v, vddq=1.8v, ta=25 o c) * dm is internally loaded to match dq and dqs identically. parameter symbol min max min max min max units non-ecc m470t6554ez3 m470t3354ez3 m470t2953ez3 input capacitance, ck and ck cck - 32 - 24 - 48 pf input capacitance, cke , cs , addr, ras , cas , we ci - 34 - 34 - 42 input/output capacitance, dq, dm, dqs, dqs cio(400/533) - 10 - 6 - 10 cio(667/800) - 9 - 5.5 - 9 speed ddr2-800(e7) ddr2-800(f7) ddr2-667(e6) ddr2-533(d5) ddr2-400(cc) units bin (cl - trcd - trp) 5 - 5 - 5 6 - 6- 6 5 - 5 - 5 4 - 4 - 4 3 - 3 - 3 parameter min max min max min max min max min max tck, cl=3 5 8 - - 5 8 5 8 5 8 ns tck, cl=4 3.75 8 3.75 8 3.75 8 3.75 8 5 8 ns tck, cl=5 2.5 8 3 8 3 8 3.75 8 - - ns tck, cl=6 - - 2.5 8 - - - - - - ns trcd 12.5 - 15 - 15 - 15 - 15 - ns trp 12.5 - 15 - 15 - 15 - 15 - ns trc 57.5 - 60 - 60 - 60 - 55 - ns tras 45 70000 45 70000 45 70000 45 70000 40 70000 ns 13.0 electrical char acteristics & ac timi ng for ddr2-800/667/533/400 (0 c < t oper < 95 c; v ddq = 1.8v + 0.1v; v dd = 1.8v + 0.1v) 13.1 refresh parameters by device density parameter symbol 256mb 512mb 1gb 2gb 4gb units refresh to active/refresh command time trfc 75 105 127.5 195 327.5 ns average periodic refresh interval trefi 0 c t case 85 c 7.8 7.8 7.8 7.8 7.8 s 85 c < t case 95 c 3.9 3.9 3.9 3.9 3.9 s 13.2 speed bins and cl, trcd, trp, trc and tras for corresponding bin 12.0 input/output capacitance
rev. 1.4 april 2007 ddr2 sdram sodimm 16 of 20 parameter symbol ddr2-800 ddr2-667 ddr2-533 ddr2-400 units notes min max min max min max min max dq output access time from ck/ck tac - 400 400 -450 +450 -500 +500 -600 +600 ps dqs output access time from ck/ck tdqsck - 350 350 -400 +400 -450 +450 -500 +500 ps ck high-level width tch 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tck ck low-level width tcl 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tck ck half period thp min(tcl,t ch) x min(tcl, tch) x min(tcl, tch) x min(tcl, tch) x ps clock cycle time, cl=x tck 2500 8000 3000 8000 3750 8000 5000 8000 ps dq and dm input hold time tdh(base) 125 x 175 x 225 x 275 x ps dq and dm input setup time tds(base) 50 x 100 x 100 x 150 x ps control & address input pulse width for each input tipw 0.6 x 0.6 x 0.6 x0.6 x tck dq and dm input pulse width for each input tdipw 0.35 x 0.35 x 0.35 x0.35 x tck data-out high-impedance time from ck/ck thz x tac max x tac max x tac max x tac max ps dqs low-impedance time from ck/ck tlz(dqs) tac min tac max tac min tac max tac min tac max tac min tac max ps dq low-impedance time from ck/ck tlz(dq) 2* tac min tac max 2*tac min tac max 2* tacmin tac max 2* tacmin tac max ps dqs-dq skew for dqs and associated dq signals tdqsq x 200 x 240 x 300 x 350 ps dq hold skew factor tqhs x 300 x 340 x 400 x 450 ps dq/dqs output hold time from dqs tqh thp - tqhs x thp - tqhs x thp - tqhs x thp - tqhs x ps write command to first dqs latching transition tdqss - 0.25 0.25 -0.25 0.25 -0.25 0.25 -0.25 0.25 tck dqs input high pulse width tdqsh 0.35 x 0.35 x 0.35 x 0.35 x tck dqs input low pulse width tdqsl 0.35 x 0.35 x 0.35 x 0.35 x tck dqs falling edge to ck setup time tdss 0.2 x 0.2 x 0.2 x 0.2 x tck dqs falling edge hold time from ck tdsh 0.2 x 0.2 x 0.2 x 0.2 x tck mode register set command cycle time tmrd 2 x 2 x 2 x 2 x tck write postamble twpst 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tck write preamble twpre 0.35 x 0.35 x 0.35 x 0.35 x tck address and control input hold time tih(base) 250 x 275 x375 x 475 x ps address and control input setup time tis(base) 175 x 200 x250 x 350 x ps read preamble trpre 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 tck read postamble trpst 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tck active to active command period for 1kb page size products trrd 7.5 x 7.5 x7.5 x 7.5 x ns active to active command period for 2kb page size products trrd 10 x 10 x10 x 10 x ns four activate window for 1kb page size products tfaw 35 37.5 37.5 37.5 ns four activate window for 2kb page size products tfaw 45 50 50 50 ns cas to cas command delay tccd 2 x 2 2 2 tck write recovery time twr 15 x 15 x15 x 15 x ns auto precharge write recovery + precharge time tdal wr+trp x wr+trp x wr+trp x wr+trp x tck internal write to read command delay twtr 7.5 7.5 x7.5 x10 x ns internal read to precharge command delay trtp 7.5 7.5 7.5 7.5 ns exit self refresh to a non-read command txsnr trfc + 10 trfc + 10 trfc + 10 trfc + 10 ns exit self refresh to a read command txsrd 200 x 200 200 200 tck exit precharge power down to any non-read command txp 2 x 2 x 2 x 2 x tck 13.3 timing parameters by speed grade
rev. 1.4 april 2007 ddr2 sdram sodimm 17 of 20 parameter symbol ddr2-800 ddr2-667 ddr2-533 ddr2-400 units notes min max min max min max min max exit active power down to read command txard 2 x 2 x 2 x 2 x tck exit active power down to read command (slow exit, lower power) txards 8 - al 7 - al 6 - al 6 - al tck cke minimum pulse width (high and low pulse width) tcke 3 3 33 tck odt turn-on delay taond 22222222tck odt turn-on taon tac(min) tac(max) + 0.7 tac(min) tac(max) +0.7 tac(min) tac(max) +1 tac(min) tac(max) +1 ns odt turn-on(power-down mode) taonpd tac(min)+ 2 2tck + tac(max) +1 tac(min)+ 2 2tck+tac (max)+1 tac(min)+ 2 2tck+ta c(max)+ 1 tac(min)+ 2 2tck+tac (max)+1 ns odt turn-off delay taofd 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 tck odt turn-off taof tac(min) tac(max) + 0.6 tac(min) tac(max) + 0.6 tac(min) tac(max)+ 0.6 tac(min) tac(max)+ 0.6 ns odt turn-off (power-down mode) taofpd tac(min)+ 2 2.5tck + tac(max) +1 tac(min)+ 2 2.5tck+ tac(max) +1 tac(min)+ 2 2.5tck+ tac(max) +1 tac(min)+ 2 2.5tck+ tac(max) +1 ns odt to power down entry latency tanpd 3 3 3 3 tck odt power down exit latency taxpd 8 8 8 8 tck ocd drive mode output delay toit 0 12 0 12 0 12 0 12 ns minimum time clocks remains on after cke asynchronously drops low tdelay tis+tck +tih tis+tck +tih tis+tck +tih tis+tck +tih ns
rev. 1.4 april 2007 ddr2 sdram sodimm 18 of 20 the used device is 32m x16 ddr2 sdram, fbga. ddr2 sdram part no : k4t51163qe 67.60 0.15 mm 4.00 0.10 20.00 0.15 mm 30.00 0.15 mm 1 199 11.40 0.15 mm 47.40 0.15 mm 6.00 0.15 mm spd a 63.00 0.15 mm 16.25 0.15 mm min 2.00 67.60 0.15 mm 30.00 0.15 mm 2200 a b 4.20 0.15 2.70 0.10 4.00 0.10 1.0 0.05 1.50 0.10 front side 4.20 0.15 1.80 0.10 4.00 0.10 1.0 0.05 2.40 0.10 back side 0.60 0.15 0.45 0.03 2.55 0.15 0.20 0.15 detail a detail b 3.8 mm max 1.1 mm max 14.1 32mbx16 based 32mx64 module (1 rank) 14.0 physical dimensions : - m470t3354ez3 units : millimeters
rev. 1.4 april 2007 ddr2 sdram sodimm 19 of 20 the used device is 32m x16 ddr2 sdram, fbga. ddr2 sdram part no : k4t51163qe 67.60 0.15 mm 4.00 0.10 20.00 0.15 mm 30.00 0.15 mm 1 199 11.40 0.15 mm 47.40 0.15 mm 6.00 0.15 mm spd 3.8 mm max 1.1 mm max a 63.00 0.15 mm 16.25 0.15 mm min 2.00 67.60 0.15 mm 30.00 0.15 mm 2200 4.20 0.15 2.70 0.10 4.00 0.10 1.0 0.05 1.50 0.10 front side 4.20 0.15 1.80 0.10 4.00 0.10 1.0 0.05 2.40 0.10 back side 0.60 0.15 0.45 0.03 2.55 0.15 0.20 0.15 detail a detail b a b 14.2 32mbx16 based 64mx64 module(2 rank) - m470t6554ez3 units : millimeters
rev. 1.4 april 2007 ddr2 sdram sodimm 20 of 20 the used device is 64m x8 ddr2 sdram, fbga. ddr2 sdram part no : k4t51083qe 3.8 mm 1.1mm max max 67.60 0.15 mm 4.00 0.10 20.00 0.15 mm 30.00 0.15 mm 1 199 11.40 0.15 mm 47.40 0.15 mm 6.00 0.15 mm 63.00 0.15 mm 16.25 0.15 mm min 2.00 67.60 0.15 mm 30.00 0.15 mm 2200 spd a b a 4.20 0.15 2.70 0.10 4.00 0.10 1.0 0.05 1.50 0.10 front side 4.20 0.15 1.80 0.10 4.00 0.10 1.0 0.05 2.40 0.10 back side 0.60 0.15 0.45 0.03 2.55 0.15 0.20 0.15 detail a detail b 14.3 64mbx8 based 128mx64 module(2 ranks) - m470t2953ez3 units : millimeters

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